Sensitive LPG Leakage Alarm

Here is an ultra-sensitive LPG sensor that generates loud beeps when it senses any gas leakage. It detects vapours of liquefied petroleum gas anywhere between 200 and 10,000 ppm and drives a piezobuzzer to catch attention for immediate action. The buzzer beeps until the concentration of gas in the air decreases to a safe level. The circuit uses an MQ6 gas sensor, which is designed to sense LPG, propane and isobutane gases.

Circuit and working
Fig. 1 shows the circuit of the LPG sensor. The circuit is built around 5V voltage regulator 7805 (IC1), gas sensor MQ6 (GS1), counter IC 4060 (IC2) and a few discrete components.GS1 is a six-pin gas sensor that can detect very small traces of LPG in the air and has a swift response time. However, it has very less sensitivity to alcohol and smoke. The sensor’s output is in the form of resistance.

As indicated in Fig. 1, the pins of GSI are H, A and B, two each on either side. H pins are for the heater with no polarity. Input pins A or B and output pins A or B can be connected either way round.The coil heater inside the sensor can be easily heated with 5V DC. If pin A is connected to 5V DC through variable resistor VR1, use pin B as the output or vice versa. Both A and B pins can be shorted. In short, H pins are connected to positive and negative rails, A or B pin to 5V DC, and B or A for output.The resistance value of GSI is different for various kinds and concentration of gases. So when using this sensor, sensitivity arrangement is very important. For accurate detection, it is necessary to calibrate the sensor for 1000 ppm of LPG concentration in the air with load resistance of about 20 kilo-ohms. (In the datasheet, the load resistance range of MQ6 is mentioned as 10 kilo-ohms to 47 kilo-ohms.)

Preset VR1 is used to adjust the sensitivity of the sensor to a particular gas concentration. Output from the sensor is connected to the base of transistor T1, which acts as a switch to trigger the alarm generator built around IC2.IC2 is a binary counter IC that oscillates using capacitor C2 and resistor R5. Transistor T1 controls the reset pin (pin 12) of IC2. When the reset pin is high IC2 does not oscillate, and when this pin goes low IC2 starts oscillating.Working of the circuit is simple. When the sensor detects LPG in the air, its output becomes high and transistor T1 conducts to make reset pin of IC2 low. This triggers IC2 to oscillate, which is indicated by LED1. After a few seconds, the buzzer starts beeping to indicate gas leakage.The circuit works off 12V DC from a battery (BATT.1) or you can use an adaptor. IC1 provides regulated 5V DC supply for the sensor and IC2.

Construction and testing
An actual-size, single-side PCB for sensitive LPG sensor is shown in Fig. 2 and its component layout in Fig. 3. After assembling the circuit on a PCB, enclose it in a suitable case with an opening to allow the gas to enter. Place the unit near the LPG cylinder or gas stove within a distance of one metre. Vary preset VR1 to adjust the sensitivity of the sensor.To test the circuit, check 12V at test point TP1 with respect to TP0 to verify the correct power supply. Place the unit near the gas stove burner and turn on the burner for a few seconds without igniting. Then, turn ’the burner ‘off’ and adjust VR1 until you see LED1 glowing. TP3 should be low at this moment.

Single chip metal detector circuit

This is a simple single chip metal detector circuit based on IC CS209A from the Cherry Semiconductors. A 100uH coil is used to sense the presence of metal. The IC CS209A has a built in oscillator circuit and the coil L1 forms a part of its external LC circuit which determines the frequency of oscillation. The inductance of the coil change in the presence of metals and the resultant change in oscillation is demodulated to create an alarm. The LED gives a visual indication too. This circuit can sense metals up to a distance of few inches.

Note:

• Assemble the circuit on a general purpose PCB.
• The switch S1 can be a slide type ON/OFF switch.
• The IC must be mounted on a holder.
• The POT R1 can be used to adjust the sensitivity of the circuit.

Add-On Stereo channel selector

The add-on circuit presented here is useful for stereo systems. This circuit has provision for connecting stereo outputs from four different sources/channels as inputs and only one of them is selected/ connected to the output at any one time. When power supply is turned ‘on’, channel A (A2 and A1) is selected. If no audio is present in channel A, the circuit waits for some time and then selects the next channel (channel B), This search operation continues until it detects audio signal in one of the channels. The inter-channel wait or delay time can be adjusted with the help of preset VR1. If still longer time is needed, one may replace capacitor C1 with a capacitor of higher value. Suppose channel A is connected to a tape recorder and channel B is connected to a radio receiver. If initially channel A is selected, the audio from the tape recorder will be present at the output. After the tape is played completely, or if there is sufficient pause between consecutive recordings, the circuit automatically switches over to the output from the radio receiver. To manually skip over from one (selected) active channel, simply push the skip switch (S1) momentarily once or more, until the desired channel inputs gets selected. The selected channel (A, B, C, or D) is indicated by the glowing of corresponding LED (LED11, LED12, LED13, or LED14 respectively). IC CD4066 contains four analogue switches. These switches are connected to four separate channels. For stereo operation, two similar CD4066 ICs are used as shown in the circuit. These analogue switches are controlled by IC CD4017 outputs. CD4017 is a 10-bit ring counter IC. Since only one of its outputs is high at any instant, only one switch will be closed at a time. IC CD4017 is configured as a 4-bit ring counter by connecting the fifth output Q4 (pin 10) to the reset pin. Capacitor C5 in conjunction with resistor R6 forms a power-on-reset circuit for IC2, so that on initial switching ‘on’ of the power supply, output Q0 (pin 3) is always ‘high’. The clock signal to CD4017 is provided by IC1 (NE555) which acts as an astable multivibrator when transistor T1 is in cut-off state. IC5 (KA2281) is used here for not only indicating the audio levels of the selected stereo channel, but also for forward biasing transistor T1. As soon as a specific threshold audio level is detected in a selected channel, pin 7 and/ or pin 10 of IC5 goes ‘low’. This low level is coupled to the base of transistor T1, through diode-resistor combination of D2-R1/D3-R22. As a result, transistor T1 conducts and causes output of IC1 to remain ‘low’ (disabled) as long as the selected channel output exceeds the preset audio threshold level. Presets VR2 and VR3 have been included for adjustment of individual audio threshold levels of left stereo channels, as desired. Once the multivibrator action of IC1 is disabled, output of IC2 does not change further. Hence, searching through the channels continues until it receives an audio signal exceeding the preset threshold value. The skip switch S1 is used to skip a channel even if audio is present in the selected channel. The number of channels can be easily extended up to ten, by using additional 4066 ICs.

ACCURATE ELECTRONIC STOP-WATCH

Here is a simple circuit which can be used as an accurate stop-watch to count up to 100 seconds with a resolution of 0.01 second or up to 1000 seconds with a resolution of 0.1 second. This stop-watch can be used for sports and similar other activities. A 1MHz crystal generates stable frequency which is divided by two stages of 74390 ICs (dual decade counter) and another stage employing 7490 (decade counter) IC to obtain a final frequency of 100 Hz or 10 Hz. Due to the use of crystal, the final frequency is very accurate. The output of IC4 (7490) is counted and displayed using IC5 74C926 (4-digit counter with multiplexed 7-segment LED driver). Due to multiplexed display the power consumption is very low. Switch S2 (2-pole, 2-way) is used to select appropriate input frequency and corresponding decimal point position to display up to either 99.99 seconds or 999.9 seconds maximum count. For proper operation, first press switch S3 (reset) and then operate switch S2, according to the resolution/range desired (0.1 sec. or 0.01 sec.)/(100 seconds or 1000 seconds). Now to start counting, press switch S1. To stop counting, press switch S1 again. The counting will stop and display will show the correct time elapsed since the start of counting.

VISUAL AC MAINS VOLTAGE INDICATOR

You should not be surprised if someone tells you that the mains voltage fluctuation could be anywhere from 160 volts to 270 volts. Although majority of our electrical and electronics appliances have some kind of voltage stabilisation internally built-in, more than 90 per cent of the faults in these appliances occur due to these power fluctuations. This simple test gadget gives visual indication of AC mains voltage from 160 volts to 270 volts in steps of 10 volts. There are twelve LEDs numbered LED1 to LED12 to indicate the voltage level. For input AC mains voltage of less than 160 volts, all the LEDs remain off. LED1 glows when the voltage reaches 160 volts, LED2 glows when the voltage reaches 170 volts and so on. The number of LEDs that glow keeps increasing with every additional 10 volts. When the input voltage reaches 270 volts, all the LEDs glow. The circuit basically comprises three LM339 comparators (IC1, IC2 and IC3) and a 12V regulator (IC4). It is powered by regulated 12V DC. For power supply, mains 230V AC is stepped down to 15V AC by stepdown transformer X1, rectified by a bridge rectifier comprising diodes D1 through D4, filtered by capacitor C4 and regulated by IC4. The input voltage of the regulator is also fed to the inverting inputs of gates N1 through N12 for controlling the level of the AC. The LED-based display circuit is built around quad op-amp comparators IC1 through IC3. The inverting input of all the comparators is fed with the unregulated DC voltage, which is proportional to mains input, whereas the non-inverting inputs are derived from regulated output of IC4 through a series network of precision resistors to serve as reference DC voltages. Resistors R13 to R25 are chosen such that the reference voltage at points 1 to 12 is 0.93V, 1.87V, 2.80V, 3.73V, 4.67V, 5.60V, 6.53V, 7.46V, 8.40V, 9.33V, 10.27V and 11.20V, respectively. When the input voltage varies from 160V AC to 270V AC, the DC voltage at the anode of ZD1 also varies accordingly. With input voltage varying from 160V to 270V, the output across filter capacitors C1 and C2 varies from 14.3V to 24.1V approximately. Zener ZD1 is used to drop fixed 12V and apply proportional voltages to all comparator stages (inverting pins). Whenever the voltage at the non-inverting input of the comparators goes high, the LED connected at the output glows. Assemble the circuit on a general purpose PCB such that all the LEDs make a bargraph. In the bargraph, mark LED1 for minimum level of 160V, then LED2 for 170V and so on. Finally, mark LED12 for maximum level of 270V. Now your test gadget is ready to use. For measuring the AC voltage, simply plug the gadget into the mains AC measuring point, press switch S1 and observe the bargraph built around LEDs. Let’s assume that LED1 through LED6 glow. The measured voltage in this case is 220V. Similarly, if all the LEDs glow, it means that the voltage is more than 270V.

A HIERARCHICAL PRIORITY ENCODER

A normal priority encoder encodes only the highest-order data line. But in many situations, not only the highest but the second-highest priority information is also needed. The circuit presented here encodes both the highest-priority information as well as the second-highest priority information of an 8-line incoming data. The circuit uses the standard octal priority encoder 74148 that is an 8-line-to-3-line (4-2-1) binary encoder with active-‘low’ data inputs and outputs. The first encoder (IC1) generates the highest-priority value, say, F. The active- ‘low’ output (A0, A1, A2) of IC1 is inverted by gates N9 through N11 and fed to a 3-line-to-8-line decoder (74138) that requires active-‘high’ inputs. The decoded outputs are active-‘low’. The decoder identifies the highest-priority data line and that data value is cancelled using XNOR gates (N1 through N8) to retain the second- highest priority value that is generated by the second encoder. To understand the logic, let the incoming data lines be denoted as L0 to L7. Lp is the highest-priority line (active-‘low’) and Lq the second highest priority line (active-‘low’). Thus Lp=0 and Lq=0. All lines above Lp and also between Lp and Lq (denoted as Lj) are at logic 1. All lines below Lq logic state are irrelevant, i.e. ‘don’t care’. Here p is the highest-priority value and q the second-highest-priority value. (Obviously, q has to be lower than p, and the minimum possible value for p is taken as ‘1’.) Priority encoder IC1 generates binary output F2, F1, F0, which represents the value of p in active-‘low’ format. The complemented F2, F1, and F0 are applied to 3-line-to-8-line (one out of eight outputs is active-‘low’) decoder 74138. Let the output lines of 74138 be denoted as M0 through M7. Now only one line is active-‘low’ among M0 through M7, and that is Mp (where the value of p is explained as above). Therefore the logic level of line Mp is ‘0’ and that of all other M lines ‘1’. The highest-priority line is cancelled using eight XNOR gates as shown in the figure. Let the output lines from XNOR gates be N0 through N7. Consider inputs Lp and Mp of the corresponding XNOR gate. Since Mp = 0 and also Lp = 0, the output of this XNOR gate is Np = complement of Lp = 1. All other L’s are not changed because the corresponding M’s are all 1’s. Thus data lines N0 through N7 are same as L0 through L7, except that the highest-priority level in L0 through L7 is cancelled in N0 through N7. The highest-priority level in N0 through N7 is the second-highest priority Left over from L0 through L7, i.e. Nq=0 and Nj=1 for q

For example, let L0 through L7 = X X X 0 1 1 0 1. Here the highest ‘0’ line is L6 and the next highest is L3 (X denotes ‘don’t care’). Thus p=6 and q=3. Now the active-‘low’ output of the first priority encoder will be F2 F1 F0 = 0 0 1. The input to 74138 is 1 1 0 and it outputs M0 through M7 = 1 1 1 1 1 1 0 1. Since M6=0, only L6 is complemented by XNOR gates. Thus the outputs of XNORs are N0 through N7 = X X X 0 1 1 1 1. Now N3=0 and the highest priority for ‘N’ is 3. This value is recovered by priority encoder 2 (IC3) as S2 S1 S0 = 1 0 0.

40-Metre Direct Conversion Receiver

Using the circuit of direct-conversion receiver described here, one can listen to amateur radio QSO signals in CW as well as in SSB mode in the 40-metre band. The circuit makes use of three n-channel FETs (BFW10). The first FET (T1) performs the function of ant./RF amplifier-cum-product detector, while the second and third FETs (T2 and T3) together form a VFO (variable frequency oscillator) whose output is injected into the gate of first FET (T1) through 10pF capacitor C16. The VFO is tuned to a frequency which differs from the incoming CW signal frequency by about 1 kHz to produce a beat frequency note in the audio range at the output of transformer X1, which is an audio driver transformer of the type used in transistor radios. The audio output from transformer X1 is connected to the input of audio amplifier built around IC1 (TBA820M) via volume control VR1. An audio output from the AF amplifier is connected to an 8-ohm, 1-watt speaker. The receiver can be powered by a 12-volt power-supply, capable of sourcing around 250mA current. Audio output stage can be substituted with a readymade L-plate audio output circuit used in transistor amplifiers, if desired. The necessary data regarding the coils used in the circuit is given in the circuit diagram itself.